Device Family: Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller Supporting UniPHY

How does UniPHY-based DDR3 controller assert the refresh command for multiple chip selects interface?

Description

The UniPHY-based memory controller does not issue the refresh command to all the chips of a multi-chip memory device or DIMM on the same clock cycle.

For example, for a four chip select case, it will assert refreshes to CS0 and CS2 in one clock cycle, followed by CS1 and CS3 in the next cycle.

The assertion of all of the chip select signals in the same clock cycle is reserved for use per memory vendor's discretion.

Workaround/Fix