This error may occur during synthesis when the afi_reset_n signal of a slave controller is not connected to the master controller's afi_reset_n output.
Device Family: Arria® II GX
Device Family: Arria® II GZ
Device Family: Arria® V GT
Device Family: Arria® V GX
Device Family: Arria® V GZ
Device Family: Arria® V ST
Device Family: Arria® V SX
Device Family: Cyclone® V E
Device Family: Cyclone® V GT
Device Family: Cyclone® V GX
Device Family: Cyclone® V SE
Device Family: Cyclone® V ST
Device Family: Cyclone® V SX
Device Family: Stratix® III
Device Family: Stratix® IV E
Device Family: Stratix® IV GT
Device Family: Stratix® IV GX
Device Family: Stratix® V E
Device Family: Stratix® V GS
Device Family: Stratix® V GT
Device Family: Stratix® V GX
Type: Answers
Area: EMIF
Area: Intellectual Property
IP Product: RLDRAM II Controller with UniPHY
Error (129036): Output port DATAOUT on atom "<slave DQS signal>", which is a arriav_delay_chain primitive, is not connected to a valid destination
Description
Workaround/Fix
Connect the afi_reset_n of the slave controller to the master controller\'s afi_reset_n output.