Device Family: Arria® II GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: Arria II GX FPGA Development Kit (RoHS) - 6G Edition (2AGX260N)

External Memory Interface Handbook: Known Issues

Description

Note on page 582 (4-6) incorrectly states the following:

Issue : Volume 3: Reference Material Chapter -  4: Functional Description—HPC II Controller

Half-Rate Bridge

Half-rate bridge support is available for ALTMEMPHY-based cores targeting device families other than Arria® II GX. Half-rate bridge support is not available for UniPHY-based cores.

When using the half-rate bridge feature, you must ensure that the local_size data for each write command remains constant until the next write command is issued. In other words, the local_size bus should not be allowed to change unless the burst_begin signal is high.

Workaround/Fix

Issue: Volume 3: Reference Material Chapter - 4:Functional Description - HPC II Controller

 

Half-rate bridge support is available for ALTMEMPHY-based cores targeting device
families other than Arria II GX. Half-rate bridge support is not available for UniPHY-based cores.

 

When using the half-rate bridge feature, you must ensure that the local_size data for
each write/read request from the local side remains constant until the next write/read request.
It is also required that the burst_begin signal from the local side must always go high for one clock cycle together with a write/read request and local_ready signal.