Device Family: Cyclone® IV E

Type: Answers

Area: EMIF, Intellectual Property

IP Product: DDR3 SDRAM Controller supporting ALTMEMPHY

Critical Warning: Pin mem_clk[0] must have its Cyclone IV E Input Delay from Pin to Internal Cells set to 1


You might get this warning in TimeQuest when implementing DDR2 High Performance Controller in Cyclone IV device using Quartus II software version 10.0 and earlier, and if your design is implemented in hybrid mode, for example, DQ pins on both side and row IOs and the “mem_clk” is placed on the side I/Os, the delay chain for the clock pin has to be set to 1. Therefore, you see this critical warning.

To remove this critical warning, add the following assignment to QSF file:

set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to mem_clk[0]

This problem is fixed in the Quartus® II software version 10.1.