Device Family: Intel® Arria® 10 GT, Intel® Arria® 10 GX, Intel® Arria® 10 SX
Area: Component, EMIF
The error message appears because the PLL reference clock setting does not meet the I/O PLL requirements. For further details, refer to the erratum New Restrictions on I/O PLL Configuration Imposed in 15.1 for Arria 10 EMIF IP
You will need to apply a higher PLL reference clock frequency setting to meet the I/O PLL performance.