Device Family: Stratix® III, Stratix® IV E, Stratix® IV GT, Stratix® IV GX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property

IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why are the Avalon byte enables not implemented in my DDR3 UniPHY controller version 11.0?


After generating a DDR3 UniPHY controller version 11.0 with the "Enable Avalon-MM byte-enable signal" selected, you may notice that the Avalon byte enable signals are not implemented.

There is a known issue where the "Enable Avalon-MM byte-enable signal" checkbox does not affect the presence or absence of the Avalon byte enables. Instead, the presence or absence of the Avalon byte enables matches the setting of the "Enable DM pins" checkbox under the Memory Parameters tab.


The workaround is to use the "Enable DM pins" checkbox to affect the state of the Avalon byte enable signals. Check "Enable DM pins" if you want the Avalon byte enables implemented or uncheck "Enable DM pins" if you do not want the Avalon byte enables implemented.

This issue is fixed in the Quartus® II software version 11.1 and later.