Device Family: Stratix® III, Stratix® IV E, Stratix® IV GT, Stratix® IV GX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property

IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Can I disable option "Enable Avalon-MM byte-enable signals" when implementing DDR3 SDRAM UniPHY based controller IP in Qsys?


When using a DDR3 UniPHY controller version 11.1 in your Qsys system if you disable the option "Enable Avalon-MM byte-enable signals", you may notice that there are no byte enables on the Avalon bus. The existence of the Avalon byte enables depends on this option. This option is checked by default but may be unchecked if no byte enables are desired.

It is not recommended to disable the Avalon byte enables in a Qsys system, especially in a mixed-width system or when masters can perform partial word accesses, because it can lead to potential data corruption problems.