It is due to the reason that the initial data with SOP loss from Avalon®-ST TX FIFO to MAC transmit control. Clock enable signal from PCS causes the Avalon-ST FIFO output to change earlier before the MAC transmit control is able to sample the first data of the first frame.
The following patch provides a solution to mask off the first read enable to the Avalon-ST FIFO in order for the first data with SOP being able to be sampled by the MAC transmit control logic.
Please download the appropriate Quartus® II software version 10.0SP1 patch 1.210 from the following links:
You must either have previously installed the Quartus II 10.0 SP1 software or must install the Quartus II 10.0 SP1 software before installing this patch. Otherwise, the patch will not be installed correctly and the Quartus II software will not run properly.
After you install the patch please regenerate your Triple Speed Ethernet MegaCore® before you compile your design.