Device Family: Arria® II GX, Arria® GX, Cyclone® IV GX, Stratix® II GX, Stratix® IV GT, Stratix® IV GX, Stratix® GX

Type: Answers

Area: Intellectual Property


Last Modified: July 16, 2019
Version Found: v10.1
Version Fixed: v11.0
IP Product: PCI Express 1/2/4/8 Lanes (x8)
Bug ID: 361722

Why doesn't the Soft IP PCIe* core send my Avalon®-MM memory read request to PCIe* bus?

Description

Due to a bug in Soft IP PCIe* generated by SOPC builder, the core may not send memory read request (MRD) to PCIe* bus although it is presented correctly on Avalon®-MM interface.

This issue does not affect Soft IP with Avalon®-ST interface or any Hard IP PCIe* cores.

If you are using Quartus® II software version 10.1, you can download download and install the following patch to resolve this issue.

Currently there is no workaround for earlier Quartus® II software versions. If using an earlier version of the Quartus® II tools, Intel® recommend moving to Quartus® II version 11.0 software.