Device Family: Stratix® V E

Device Family: Stratix® V GS

Device Family: Stratix® V GT

Device Family: Stratix® V GX

Type: Answers

Area: EMIF

Area: Intellectual Property


IP Product: QDRII SRAM Controller

Does Stratix V QDRII/+ SDRAM Controller at full rate have timing closure issue?

Description

Yes, you might experience out of box timing violations with Stratix® V QDRII/+ at full rate. This issue will be fixed in a future Quartus® II software and IP version.

Workaround/Fix

To workaround this issue, in the SDC file locate these lines:

                if {} {

                                set_clock_uncertainty -to [get_clocks _*] -add -hold 0.200

                                set_clock_uncertainty -to [get_clocks _*] -add -hold 0.100

                                set_clock_uncertainty -to [get_clocks _*] -add -hold 0.160

                }

and change them to

                if {} {

                                set_clock_uncertainty -to [get_clocks _*] -add -hold 0.400

                                set_clock_uncertainty -to [get_clocks _*] -add -hold 0.150

                                set_clock_uncertainty -to [get_clocks _*] -add -hold 0.225

 

                                set_clock_uncertainty -to [get_clocks _*] -add -setup 0.200

                }