Device Family: Stratix® IV GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: QDRII SRAM Controller

Which pin assignment guideline should I use for QDR II SRAM with read latency of 1.5?

Description

For QDR II SRAM with 1.5 read latency, use the same pin assignment guideline for QDR II SRAM with 2.5 latency. The pin assignment guideline for the QDRII SRAM device with 2.5 cycle latency is given in table 2-9 in the External Memory Interface Handbook chapter Device and Pin Planning (PDF).

Connect the complement clock (CQn) pin to the CQn pin (not the DQSn pin) and CQ pin to the DQS pin on the device.