Device Family: Stratix® V, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

How do I take the package delay into account in the board skew parameters of a Stratix V DDR3 UniPHY controller GUI?

Description

For DDR3 UniPHY designs with frequencies greater than 533MHz, you must take into account FPGA package delays when determining trace-length matching. For DDR3 UniPHY designs running at 533MHz or below, you do not take the package delays into account.

To get the package delays, you need to check the “Package deskew” checkbox in the DDR3 UniPHY Megawizard Board Settings tab and compile the design as normal with a specific pinout. The package delays for the traces that require accounting for the package will be displayed in the Package Delay column of the .pin file.  Additionally, when “Package deskew” is checked, Quartus II will assume that you will be deskewing the device package skew on your board and will not use this number for timing analysis.

You will need to deskew the package delays with the board traces for your design for DQ, DM and DQS signals. For example if the package delay on three pins reported in the .pin file is

Pin A    120ps
Pin B    80ps
Pin C    160ps

You would have to have a board trace for Pin A that is 40ps longer than Pin C, and a board trace for Pin B that is 80ps longer than Pin C.

When entering the board skews into the DDR3 UniPHY Megawizard Board Settings tab, you should use the board delay + package delay when calculating the board skew parameters. If a pin does not have a package delay, then you must use the board delay only.

If Quartus® II software does not report these package delays in the .pin file, go to the Net Length Reports page from the Altera Board Design Resource Center (Refer to the related solution rd07122010_270 below for more details on how to get the package trace lengths).