Type: Answers

Area: EMIF

Area: Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why do I always see read capture timing failure in one of the DDR2/DDR3 SDRAM UniPHY based memory controllers when I have multiple instantiations of DDR2/DDR3 SDRAM UniPHY based memory controller in my design?

Description

There is a knownissue in Quartus® II software version 10.0 when the same UniPHY core is instantiated more than once. An issuein sdc timing script causes incorrect input max delay to be set so read capture fails because of it.

Thisissue is already fixed in Quartus II software10.1. follow the steps below for 10.0 to fix the issue.

1. Open <core>.sdc file in a text editor.

2. Find the “for” loop inside which all instances of the core are constrained by search text “foreach { inst } $instances”.

3. Inside the this “for” loop, scroll down to “QUERIED TIMING” section, and find these 2 lines;

set data_input_max_delay [ round_3dp [ expr $data_input_max_delay + $fpga …

set data_input_min_delay [ round_3dp [ expr $data_input_min_delay - $t(CK) …

change them to:

set final_data_input_max_delay [ round_3dp [ expr $data_input_max_delay + $fpga …

set final_data_input_min_delay [ round_3dp [ expr $data_input_min_delay - $t(CK) …

4. Scroll down more inside the “for” loop, and find the lines below:

# Specifies the maximum delay difference between the DQ pin and the DQS pin:

set_input_delay -max $data_input_max_delay -clock [get_clocks …

# Specifies the minimum delay difference between the DQ pin and the DQS pin:

set_input_delay -min $data_input_min_delay -clock [get_clocks …

change them to

# Specifies the maximum delay difference between the DQ pin and the DQS pin:

set_input_delay -max $final_data_input_max_delay -clock [get_clocks …

# Specifies the minimum delay difference between the DQ pin and the DQS pin:

set_input_delay -min $final_data_input_min_delay -clock [get_clocks …

5. Save the file and recompile project, check read capture timing to make sure read timing is positive for all interfaces.