Device Family: Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX, Stratix® V, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller Supporting UniPHY

Warning (332009): The launch and latch times for the relationship between source clock: and destination clock: are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.

Description

When you compile a UniPHY-based DDR3 SDRAM controller, you may get the above warning between pll_ref_clk and pll_afi_clk/pll_write_clk.

The reason for this warning is a non-integer ratio between the PLL reference clock frequency and the operating frequency, which forces the launch and latch edge times beyond the allowed range of time values.

Workaround/Fix

The warning can be safely ignored. If you want to avoid the warning, you can try one of these two workarounds.

Workaround 1: Add a “set_false_path” constraint between pll_ref_clk and pll_afi_clk/pll_write_clk because there is no timing path between pll_ref_clk and the PLL output clocks.

Workaround 2: Change the frequency of the PLL reference clock to get an integer ratio between the PLL reference clock frequency and the operating frequency.