Device Family: Arria® II GX, Arria® II GZ, Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® III, Cyclone® III LS, Cyclone® IV E, Cyclone® IV GX, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX, Stratix® IV E, Stratix® IV GT, Stratix® IV GX, Stratix® V, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers, How-To

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

How do I decide when to compensate for the package delay mismatch (Package Deskew) when routing the board traces for my memory interface?

Description

Package deskew is not required for any memory protocol operating at 800 MHz or below. For DDR3 and RLDRAM3 design operating above 800 MHz;, Altera recommends that you should run the timing analysis with accurately entered board skew parameters in the IP megawizard. Only if you are getting non-core timing violations in the 'Report DDR' Timing report then you should apply the steps mentioned in the ‘Package Deskew’ section of Volume 2 Chapter 4 of the EMIF Handbook.  The recommendation may be different to that shown in the External  Memory Interface handbook and Altera is in the process of updating the handbook document.

Workaround/Fix