Due to a problem in the Quartus® II software ,when using the hard memory controller with UniPHY, there might be a tWPRE timing violation being observed when probing the signals with an oscilloscope. This issue occurs because the parallel termination circuitry (read OCT) does not switch to series termination mode early enough to prevent squelching of the DQS write preamble.
Device Family: Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX
Area: EMIF, Intellectual Property
IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY