Device Family: Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why do I see a DQS write preamble (tWPRE) violation in hardware when using DDR3 or DDR2 SDRAM hard memory controller with UniPHY?

Description

Due to a problem in the Quartus® II software ,when using the hard memory controller with UniPHY, there might be a tWPRE timing violation being observed when probing the signals with an oscilloscope. This issue occurs because the parallel termination circuitry (read OCT) does not switch to series termination mode early enough to prevent squelching of the DQS write preamble.

Workaround/Fix

This problem does not affect hardware operation. Please contact Altera mySupport for more details.

Related Solution

http://www.altera.com/support/kdb/solutions/fb142174.html