Article ID: 000077728 Content Type: Troubleshooting Last Reviewed: 12/20/2016

Does Intel provide support for Multi-port Front End IP implemented in the core FPGA fabric?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Multi-port Front End logic can be used to connect multiple Avalon® bus masters to a single port Avalon slave memory controller.

Currently Altera does not provide support for soft Multi-Port Front End IP with identical functionality to the hard Multi-Port Front End IP implemented in Arria® V and Cyclone® V devices.

However, these sources of information may be useful as a starting point for users who require Multi-Port Front End functionality in the FPGA core logic :

Application Notes

AN637: Sharing External Memory Bandwidth Using the Multi-Port Front-End Reference Design (PDF)

Design files for AN 637

Related Products

This article applies to 24 products

Stratix® V FPGAs
Cyclone® V GT FPGA
Stratix® V GX FPGA
Cyclone® V GX FPGA
Stratix® V GS FPGA
Arria® V GX FPGA
Stratix® V GT FPGA
Arria® V FPGAs and SoC FPGAs
Arria® V GT FPGA
Stratix® III FPGAs
Stratix® IV GX FPGA
Arria® II GX FPGA
Arria® II GZ FPGA
Stratix® IV GT FPGA
Cyclone® V E FPGA
Cyclone® V FPGAs and SoC FPGAs
Stratix® V E FPGA
Cyclone® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Cyclone® V SE SoC FPGA
Arria® V SX SoC FPGA
Arria® V ST SoC FPGA
Stratix® IV FPGAs
Stratix® IV E FPGA