Device Family: Arria® V GT, Arria® V GX, Arria® V ST, Arria® V SX, Cyclone® V

Intel Software: Quartus Prime Standard

Type: Answers

Area: EMIF

Last Modified: December 10, 2013
Version Found: v13.0 Service Pack 1
IP Product: DDR3 SDRAM Controller Supporting UniPHY
Bug ID: N/A

Why does the local_cal_success go high but local_init_done stay low during RTL simulation for the hard memory controller?


When running an RTL simulation for the UniPHY-based hard memory controller in Arria® V or Cyclone® V device, you may find local_cal_success go high but local_init_done stay low. The local_init_done signal is driven by the hard memory controller based on the internally synchronized version of the afi_cal_success input. The local_init_done and local_cal_success signals should have the same behavior. However, they may have different behaviors if the the clock input or reset input for the multi port front-end (MPFE) is not correctly connected.


Make sure the MPFE clock and reset ports are properly connected.