Device Family: Stratix® III, Stratix® IV E, Stratix® IV GT, Stratix® IV GX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: Renewal RLDRAM II Controller

Error: {instance_name}: Module has too many unassociated clocks ({instance_name}.pll_ref_clk, {instance_name}.afi_half_clk_in). Only one unassociated clock is allowed

Description

When you connect a Master Uniphy based controller with a slave Uniphy based controller to share PLL and DLL in system generated by SOPC builder, you will encounter the following error message:

Error: {instance_name}: Module has too many unassociated clocks ({instance_name}.pll_ref_clk, {instance_name}.afi_half_clk_in). Only one unassociated clock is allowed

Workaround/Fix

Uniphy PLL sharing has never been supported in SOPC Builder. Use Qsys to generate your system.

 

Untill Quartus® II software version 11.0 you could generate a system and manually connect the pll_* and dll_* signals in the RTL (since the GUI does not display these for you to connect).

 

Starting in the Quartus II software version 11.0SP1 connecting the signals manually in the RTL to share PLL and DLL will no longer work.

 

You will have to use Qsys in order to generate a system that shares PLL and DLL between multiple controllers.