Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why do I see hold time violations in Core path under "Report DDR" timing report of DDR3 SDRAM Controller with UniPHY when implementing it in HardCopy devices?

Description

You may see hold time violations in Core path in Report DDR timing report of DDR3 SDRAM Controller with UniPHY only in HardCopy® revision. This violation could happen when the pll_afi_clk (clock output c0 of the PLL) is not placed on a global clock network. Global clocks and regional clocks have larger skew in HardCopy IV device family compared to Stratix® IV device family.

Workaround/Fix

To avoid the hold timing violations, place the pll_afi_clk to a global clock network.