Type: Answers

Area: EMIF

Area: Intellectual Property


IP Product: RLDRAM II Controller with UniPHY

Critical Warning (308019): (Critical) Rule C101: Gated clock should be implemented according to the Altera standard scheme.

Description

When running the Design Assistant tool in the Quartus® II software, the following critical warning message may appear:

Critical Warning (308019): (Critical) Rule C101: Gated clock should be implemented according to the Altera standard scheme. Found 1 node(s) related to this rule.
Critical Warning (308012): Node  "<variation name>_example_if0:if0|test_rldram_example_if0_pll0:pll0|out_phyclk[0]"

Workaround/Fix

This clock is implemented in the hard logic and the warning can safely be ignored.