You will get the warning mentioned above in Quartus® II software version 10.0SP1 and earlier if you have instantited <instance_name>_example_top.v for master and slave UniPHY controllers in your design.
pll_dqs_ena_clk signal is missing in both master and slave <instance_name>_example_top.v and this will cause the critical warning in fitter report.
To avoid the above mentioned critical warning, you should add pll_dqs_ena_clk port to the <instance_name> instantiated in the <instance_name>_example_top.v files for both master and slave module.
For example, in top level design add the port pll_dqs_ena_clk as shown below:
ddr2 mem_if (
// when PHY is the PLL/DLL master, these will be outputs that can be shared with other components of the chip
// when PHY is the PLL/DLL slave, these will be inputs from the PLL/DLL instantiations below
.pll_dqs_ena_clk (pll_dqs_ena_clk), //added
This issue has been fixed in Quartus II software version 10.1.