Device Family: Intel® Arria® 10 GT, Intel® Arria® 10 GX, Intel® Arria® 10 SX, Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers, How-To

Area: Intellectual Property


IP Product: PCI Express 1/2/4/8 Lanes (x8)

How can I use VSEC registers in my Hard IP for PCI Express?

Description

The following is a framework for implementation of VSEC register usage.

Workaround/Fix

1) Set up your VSEC memory in the FPGA fabric using Internal RAM.

2) In the Altera® Vendor-Specific (VSEC) Extended Capability Header (offset 0x200), set bits [31:20] to 0x400 (reserved space for the HardIP, other reserved locations are also available)

3) Decode the TLPs that target the range 0x400 plus (+) the size of memory needed for new VSEC capability

4) Ensure VSEC memory is decoded and encoded through application layer logic