Device Family: Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: Component, EMIF


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

When does the UniPHY DDR3 IP use an I/O standard of SSTL-15 Class II ?

Description

When the UniPHY DDR3 PHY Settings tab "Memory Clock frequency" parameter is set above 800MHz, the default DDR3 interface signal I/O standard is set to SSTL-15 Class II to increase the drive strength. The memory datapath and clock signals have an Output Termination assignment of Series 25 ohm with calibration.

These assignments are applied in the standard supported flow of running the <variation_name>_p0_pin_assignments.tcl file after analysis and synthesis.

It is strongly recommended that users perform board level simulations to verify the signal integrity of their DDR3 interface.

Workaround/Fix