Article ID: 000083749 Content Type: Troubleshooting Last Reviewed: 06/30/2014

Why are the Stratix V GX RX equalization settings different between the register mapped area, and the QSF assignments?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The Stratix® V GX RX equalization settings are different between the register mapped area, and the QSF assignments due to a mistake in the PHY IP userguide.

Valid transceiver reconfiguration controller memory mapped values are 0 to 15.
Valid QSF assignments are 1 to 16.

The setting 0 in the transceiver reconfiguration controller corresponds to setting 1 in Quartus® II QSF assignment and so on.

Resolution

This discrepancy will be corrected in a future version of the PHY IP User Guide

Related Products

This article applies to 2 products

Stratix® V FPGAs
Stratix® V GX FPGA