How do I simulate the Arria 10, Arria V GZ and Stratix V PCI Express IP cores in Gen3 PIPE Mode?

Device Family: Intel® Arria® 10, Arria® V GZ, Stratix® V

Type: Answers

Area: Intellectual Property

Description

Due to a problem in the Quartus® II and the Intel® Quartus® Prime Software versions, the Intel® Arria® 10, Arria® V GZ and Stratix® V Hard IP for PCI* Express IP cores only support Gen3 PIPE simulation using the Synopsys* (VCS) simulator. To use other simulators, follow the instructions below.

Workaround/Fix

To work around this problem, follow these steps:

Replace the existing files under ...\simulation\submodules with these versions:
- altpcietb_pipe32_driver.v
- altpcietb_pipe32_hip_interface.v
Edit the`defines in each of those files to match your design hierarchy:
- In altpcietb_pipe32_hip_interface.v, replace top_tb.top_inst with your hierarchy:
  define HIP_INTERFACE top_tb.dut_pcie_tb.g_altpcie_hip_pipe32_sim_probe.altpcietb_pipe32_hip_interface
In the top-level testbench file (top_tb in this example), edit the dut_pcie_tb instantiation and set the following parameters as shown:
- serial_sim_hwtcl (0),
- enable_pipe32_sim_hwtcl (1),
- enable_pipe32_phyip_ser_driver_hwtcl (1)

This problem is not scheduled to be fixed in a future release of the Intel® Quartus® Prime or Quartus® II software.