Device Family: Arria® V GX, Cyclone® V E, Cyclone® V GX, Stratix® III, Stratix® IV E, Stratix® IV GT, Stratix® IV GX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property

IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Should I use the option "Generate power-of-2 data bus widths for Qsys or SOPC Builder" in DDR2 or DDR3 SDRAM Controller with UniPHY?


If you are using the DDR2 or DDR3 SDRAM Controller with UniPHY, select this option if the width of the SDRAM data bus is a power of 2 or if the data width is not a power of 2 and you do not intend to use the full data bus.

Selecting this option rounds down the width of the data bus. For example if you select a data width of 72 bits and the controller is set to half rate, the Avalon-MM data width will be truncated to 256. This will prevent you from using the top 32 data bits.

If you wish to use the full width of your memory, do not check the Generate power-of-2 data bus widths for Qsys or SOPC Builder option.