Type: Answers

Type: How-To

Area: EMIF

Area: Intellectual Property

IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why do I see the message "Connection between avalon_master.writedata and avl.avl_wdata must be width of [8,16,32,64,128,256,512,1024] with the DDR2(3) SDRAM Controller with UniPHY?


If the DDR2(3) SDRAM Controller with UniPHY implemented in Qsys, is configured to not use a power of 2 Avalon® data bus, only one connection can be made between the master interface and the slave interface on the DDR2(3) controller. You will see the above message if you connect 2 masters to the DDR2(3) SDRAM Controller.

If multiple connections are required to the Avalon slave interface on the DDR2(3) Controller, increase the size of the write and read data signals of the masters to a greater power of a 2 and implement a simple bus gasket (custom component) between the Master connections and the slave interface on the DDR2(3) controller. The gasket will simply pass through all signals except the write and read data.

For write data the gasket will only pass through the required number of data bits. For example if the desired memory interface is 72 bits, the half rate controller data width would be 288. The master would round up the data bus to 512 and pad the write data with 224 '0's and the gasket would simply pass through the 288 bits required.

-- send desired data bits to the DDR through gasket's master interface

avm_m0_writedata <= avs_s0_writedata(287 downto 0);

For read data the gasket will pad the top 288 bits with '0's.

-- create a pad constant

constant PAD_DATA : std_logic_vector(287 downto 0) := (others => '0');

-- send read data to the master through the gasket's slave interface

avs_s0_readdata <= PAD_DATA & avm_m0_readdata