Device Family: Intel® Arria® 10 GT, Intel® Arria® 10 GX, Intel® Arria® 10 SX, Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V GT, Cyclone® V GX, Cyclone® V ST, Cyclone® V SX, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: Intellectual Property

IP Product: PCI Express 1/2/4/8 Lanes (x8)

How can I ascertain if an autonomous PCIe HIP enters the L0 state before full fabric configuration finishes?


The autonomous PCI® Express Hard IP is capable of reaching the LTSSM L0 state before the full FPGA fabric has been loaded.

Observe the LTSSM state of the PCIe IP core using SignalTap™ II with Power-Up trigger. This Power-Up Trigger will show the Hard IP LTSSM state the moment full fabric configuration completes. Therefore all earlier LTSSM states must have been reached prior to the fabric configuration completing.

For additional detail about SignalTap II with Power-Up trigger, see following document: