Article ID: 000084593 Content Type: Troubleshooting Last Reviewed: 09/11/2012

What is the minimum pulse width of reset signal for Triple-Speed Ethernet MegaCore?

Environment

  • Reset
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    Description

    Triple-Speed Ethernet (TSE) MegaCore® IP has many clock domains. Reset signals to these clock domains are generated by synchronizing the only one reset signal of TSE IP to each clock.

    Therefore, the minimum pulse width of the input reset signal must be bigger than period width of the slowest clock used in the TSE IP.

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    Intel® Programmable Devices