Type: Answers

Area: Intellectual Property


IP Product: Triple Speed Ethernet MAC

In FIFO less mode of Triple-Speed Ethernet (TSE) IP, when will the mac_rx_clk_0 start toggling and when will it be stabled after the TSE reset signal is de-asserted?

Description

In FIFO less mode of Triple-Speed Ethernet (TSE) IP, the mac_rx_clk_0 stops toggling during the TSE IP resetting.

But Altera® does not have any specific number on when the mac_rx_clk_0 will start toggling aftre the TSE reset signal is de-asserted.

You will need to implement the clock detection circuit for mac_rx_clk_0.

In normal cases, mac_rx_clk_0 will start toggling few clocks cycle after the TSE resetting, and once the mac_rx_clk_0 is detected, it is the stable clock.