Device Family: Stratix® III, Stratix® IV E, Stratix® IV GT, Stratix® IV GX

Type: Answers

Area: EMIF, Intellectual Property



Is there any known issue that can cause calibration failure on designs with full-rate QDRII/II+ SRAM and RLDRAM II UniPHY based controller created in the Quartus II software version 10.0SP1 and earlier?

Description

Yes. All full-rate QDRII/II+ SRAM and RLDRAM II UniPHY based designs created in Quartus® II software version 10.0SP1 and earlier might encounter intermittent calibration failure in hardware. Multiple times of recalibration/reset may observe one calibration failure. Calibration failure is due to unreliable asynchronous Read FIFO reset signal transfer from the sequencer (AFI clock domain) to the read data path (read-capture clock domain).

In full-rate design, two clock cycles of Read FIFO reset signal assertion in sequencer is required to guarantee the reset signal to be captured correctly in the read data path. However, Read FIFO reset signal is only asserted for one clock cycle in the sequencer. Also, combinational logic exists in clock-cross path and causes the reset signal transfer to not be robust enough. This leads to Read FIFO is not being cleared properly during calibration.

The workaround for this issue is to install the Quartus II software patch below in Quartus II software 10.0SP1 and regenerate the IP. This issue will be fixed in future release of the Quartus II software.

Download the appropriate Quartus II software version 10.0SP1 patch 1.150 from the following links: