Device Family: Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller Supporting UniPHY

Why is the efficiency of the Cyclone V and Arria V hard memory controller lower than expected for single port designs?

Description

The Multi-Port Front End (MPFE) which is used with the Hard Memory Controller for Arria® V and Cyclone® V devices contains an arbiter which enables load balancing across multiple ports. The MPFE will always grant access to a different port after it has finished serving a port.

This behavior means that where the MPFE only receives traffic on one port, either because no other ports have pending transactions or because a single port variation is generated, the controller will implement writes in 5 clock cycles instead of 4 clock cycles. Reads are not affected.

This behavior may also be seen in multi-port MPFE configurations.

 

 

 

Workaround/Fix

There is no workaround for this behavior.