Device Family: Stratix® V, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property

IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why is my DDR3L SDRAM UniPHY based controller design missing some pin assignments?


When you run the pin_assignments.tcl file for DDR3L SDRAM UniPHY based controller design in the Quartus®  II software version 11.0sp1 and 11.1, you will see the following assignments are missing:

  • address and command signals do not have output termination assignments.
  • memory clock outputs are assigned "Series 40 ohm with Calibration" instead of "without Calibration".
  • address and command signals are using the wrong termination control block

This is a known issue in the Quartus II software version 11.1 and 11.0SP1.


The workaround is as follows:
  • assign the address and command signals to output termination of "series 40 ohm with calibration":

set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to {addr/cmd}

  • change the memory clock (mem_ck and mem_ck_n) assignments to output termination of "series 40 ohm without calibration":

set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to {mem_ck/mem_ck_n}

  • assign the address and command signals to the proper termination control block:

set_instance_assignment -name TERMINATION_CONTROL_BLOCK "{path}_p0_oct_control:uoct_control|sd1a_0" -to {addr/cmd}

Compile the design and you should see the correct assignments on the DDR3 interface pins.

This issue will be fixed in a future release of the Quartus II software.