During normal SPI4.2 transmitter operation, aN_atxdav will be de-asserted given the below conditions:
1. The remaining room available to write new data into the FIFO buffer is below the FIFO buffer threshold high (FTH) value
2. After the last successful write before a FIFO overflow, a flushing operation begins. User logic is prohibited from writing to the FIFO during this time
However, if the SPI4.2 receiver resets suddenly due to system constraint, for example a processor reset, then aN_atxdav signal of the transmitter core will be de-asserted at some point in time. The de-assertion of aN_atxdav signal for this purpose is regardless of the FIFO buffer size and "ignore backpressure" setting when you turn on shared buffer with embedded addressing. This scenerio is due to when the downstream receiver core is reset, the receiver will start sending framing pattern (2'b11) on the status channel. When the transmitter sees the status channel in framing mode, it will respond with sending training patterns (4'h000F and 4'hFFF0). Consequently, it will stop reading from the FIFO buffer. To prevent the continuous writing to the FIFO buffer aN_atxdav signal is de-asserted some time later. During this phase, the transmitter will keep sending training patterns until stat_rd_rdat_sync is asserted in the receiver core which signifies that the receiver is ready to receive data again. Thus, once receiver resets, transmitter stops sending data and goes into training mode. This inevitably causes the aN_atxdav signal to be de-asserted to prevent overflow of the FIFO buffer. When the receiver transmits valid status frames, then aN_atxdav will be asserted again.