Device Family: Arria® II GX

Device Family: Arria® II GZ

Device Family: Arria® V GT

Device Family: Arria® V GX

Device Family: Arria® V GZ

Device Family: Arria® V ST

Device Family: Arria® V SX

Device Family: Cyclone® V E

Device Family: Cyclone® V GT

Device Family: Cyclone® V GX

Device Family: Cyclone® V SE

Device Family: Cyclone® V ST

Device Family: Cyclone® V SX

Device Family: Stratix® III

Device Family: Stratix® IV E

Device Family: Stratix® IV GT

Device Family: Stratix® IV GX

Device Family: Stratix® V E

Device Family: Stratix® V GS

Device Family: Stratix® V GT

Device Family: Stratix® V GX

Type: Answers

Area: EMIF

Area: Intellectual Property


IP Product: RLDRAM II Controller with UniPHY

Critical Warning: _p0_pin_map.tcl: Failed to find PLL clock for pins

Description

You may experience the above critical warning on UniPHY designs with a master and a slave controller. The critical warning results when the PLL sharing signals are not properly connected from the master controller to the slave controller.

Workaround/Fix

Refer to the EMIF Handbook, Functional Description - UniPHY chapter, for a description on how to connect the PLL sharing signals from the PLL master to the PLL slave.