Device Family: Cyclone® V GT

Device Family: Cyclone® V GX

Device Family: Cyclone® V SE

Device Family: Cyclone® V ST

Device Family: Cyclone® V SX

Type: Answers

Area: EMIF

Area: Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Warning (177007): PLL(s) placed in location &ltPLL location&gt do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks

Description

You may see the above warning message when you compile the generated example design of the UniPHY-based DDR3 memory controller.

Workaround/Fix

This warning will show up when user doesn\'t specify whether they are willing to have feedback and output paths differently.  Quartus will try to match both paths with the same compensation path.  This warning can be fixed by setting the following QSF assignment:

set_instance_assignment -name MATCH_PLL_COMPENSATION_CLOCK OFF -to *