Due to a problem in the ALTDQ_DQS2 megafunction in the Quartus® II software, a glitch may occur at the output of the DQS logic block, which may cause random read errors when performing PVT testing. Your design is impacted if all three of the following conditions are true:
1. The custom protocol is strobe-based, where the Make capture strobe bidirectional option is enabled in the ALTDQ_DQS2 MegaWizard GUI.
2. The DQS enable block is used, where the Use capture strobe enable block option is enabled in the ALTDQ_DQS2 MegaWizard GUI (applicable for Arria® V GZ and Stratix® V families only).
3. If the memory frequency is running in the affected range:
Cyclone® V E/GX/GT/SE/SX/ST & SoC: All frequencies
Arria® V GX/GT/SX/ST & SoC: All frequencies
Arria® V GZ: < 445MHz
Stratix® V (-1/-2 speed grade): <480MHz
Stratix® V (-3/-4 speed grade): <445MHz