Device Family: Arria® V GT

Device Family: Arria® V GX

Device Family: Arria® V GZ

Device Family: Arria® V ST

Device Family: Arria® V SX

Device Family: Cyclone® V GT

Device Family: Cyclone® V GX

Device Family: Cyclone® V ST

Device Family: Cyclone® V SX

Device Family: Stratix® III

Device Family: Stratix® IV E

Device Family: Stratix® IV GT

Device Family: Stratix® IV GX

Device Family: Stratix® V E

Device Family: Stratix® V GS

Device Family: Stratix® V GT

Device Family: Stratix® V GX

Type: Answers

Area: EMIF

Area: Intellectual Property


IP Product: DDR3 SDRAM Controller supporting ALTMEMPHY

Why is afi_rlat tied to ground in my UniPHY-based PHY-Only instance of the external memory interface?

Description

The use of the afi_rlat signal is not supported for PHY-Only designs.

Workaround/Fix

The workaround is to use afi_rdata_valid signal to determine when valid read data is available.

For more information, refer to the External Memory Interface Handbook.