Article ID: 000079854 Content Type: Error Messages Last Reviewed: 05/23/2023

Warning: Port "datab" on the entity instantiation of "lpm_add_sub_component" is connected to a signal of width 32. The formal width of the signal in the module is 16. The extra bits will be ignored.

Environment

  • Quartus® II Subscription Edition
  • DSP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You will see this warning, perhaps multiple times, when you create simulation models for an NCO II Intel® FPGA IP.  You might also see the following warning message:

    Warning: Verilog HDL or VHDL warning at nco_altera_nco_ii_140_riojqbq.v(91): object "select_s" assigned a value but never read

    Resolution

    These warnings can be safely ignored, they will cause no simulation problems and do not affect the synthesis models.

     

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