Warning: Port "datab" on the entity instantiation of "lpm_add_sub_component" is connected to a signal of width 32. The formal width of the signal in the module is 16. The extra bits will be ignored.

Device Family: Intel® Arria® 10 GT

Device Family: Intel® Arria® 10 GX

Device Family: Intel® Arria® 10 SX

Device Family: Arria® V GT

Device Family: Arria® V GX

Device Family: Arria® V GZ

Device Family: Arria® V ST

Device Family: Arria® V SX

Device Family: Cyclone® V E

Device Family: Cyclone® V GT

Device Family: Cyclone® V GX

Device Family: Cyclone® V SE

Device Family: Cyclone® V ST

Device Family: Cyclone® V SX

Device Family: Stratix® V E

Device Family: Stratix® V GS

Device Family: Stratix® V GT

Device Family: Stratix® V GX

Type: Answers

Area: Intellectual Property

You will see this warning, perhaps multiple times, when you create simulation models for an NCO II MegaCore®. You may also see the following warning:

Warning: Verilog HDL or VHDL warning at nco_altera_nco_ii_140_riojqbq.v(91): object "select_s" assigned a value but never read

Description