Device Family: Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Stratix® III, Stratix® IV E, Stratix® IV GT, Stratix® IV GX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property

IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why is avl_ready stuck low in my DDR3 UniPHY-based controller in Quartus II 12.0SP2?


In the Quartus® II software version 12.0SP2, DQS tracking is enabled for DDR3 controllers operating above 533MHz in Stratix® V and 450MHz in Arria® V. When DQS tracking is enabled, a sequencer tracking manager ( is created to control the tracking. There is a problem in the file where the cfg_num_dqs signal is only 3 bits and can support up to 7 DQS groups. For DDR3 interfaces that are 64-bit (8 DQS groups) or 128-bit (16 DQS groups), the sequencer track manager will lock up causing the Avalon bus ready signal avl_ready to be stuck low.


To prevent avl_ready from getting stuck low, implement the following workaround:

  1. Open the file in a text editor
  2. Search for cfg_num_dqs and change the declaration from:
    logic [2:0] cfg_num_dqs;
    logic [AVL_DATA_WIDTH - 1:0] cfg_num_dqs;
  3. Recompile the design. The EMIF debug toolkit should run without hanging.

This probelm has been fixed with the Quartus II software version 12.1.