The following HPS Peripheral Clocks can be routed to the FPGA logic:
Due to a problem in the Quartus® II software versions 13.0 and later, if these clocks are connected to external FPGA pin directly, quartus fit may generate an error message. The following is an example for the spim1_sclk_out signal connected to an external pin:
Error (14566): Could not place 1 periphery component(s) due to conflicts with existing constraints (1 auto-promoted clock driver(s))
Error (175020): Illegal constraint of auto-promoted clock driver that is part of Arria V/Cyclone V Hard Processor System ghrd_hps_0 to the region (92, 67) to (183, 137): no valid locations in region
Info (14596): Information about the failing component:
Info (175028): The auto-promoted clock driver name: ghrd:soc_inst|ghrd_hps_0:hps_0|ghrd_hps_0_fpga_interfaces:fpga_interfaces|spim1_sclk_out~CLKENA
More information on these clocks can be found in the "Peripheral FPGA Clocks" section of the Cyclone V or Arria® V Device Handbook, Volume 3: Hard Processor System Technical Reference Manual (http://www.altera.com/literature/hb/cyclone-v/cv_5v4.pdf, page 27-12).