Device Family: Stratix® III, Stratix® IV E, Stratix® IV GT, Stratix® IV GX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why do I see discontinuity in the read data burst on mem_dq bus even when I do not change the row address during the read operation using DDR3 SDRAM UniPHY and Altmemphy based controller?

Description

When implementing DDR3 SDRAM UniPHY and Altmemphy based memory controller, user will notice that during read operation, mem_dq bus does not give continuous burst even when there is no row address change. You will see this behavior in simulation as well.

Workaround/Fix

You need to manually update CFG_RDBUFFER_ADDR_WIDTH in alt_mem_ddrx_controller.v HDL to fix it.

Set CFG_RDBUFFER_ADDR_WIDTH to:
Full rate - 8
Half rate - 7
Quarter rate - 6

This issue will be fixed in a future version of the Quartus® II software.