The method used to create a .jic file with a Nios® II hardware and software image is as follows.
1. Create a flash file from a .sof file: sof2flash --input=<hwimage>.sof --output=hwimage.flash --epcs --verbose
2. Create a flash file from a ,elf file: elf2flash --input=<elf file>.elf --output=swimage.flash --epcs --after=hwimage.flash --verbose
3. Convert the .flash image into a.hex file: nios2-elf-objcopy --input-target srec --output-target ihex mysw.flash mysw.hex
4. In the Quartus® II software, open File > Convert Programming Files > Set the programming file as JTAG Indirect Configuration File (.jic).
6. Select the correct size EPCS device in the Configuration pull-down
7. Name your output .jic file
8. Click Flash Loader below, and select Add Device on the right hand side
9. Select your FPGA device from the list
10. Click SOF Data, and select Add File, and select your .sof file
11. Click Add Hex data, select Relative addressing, and select your .hex file created above
12. Now push generate. You should verify that the generated .map file has Page_0 at a start address of 0x0, and the hex file at a start address 1 after the end address of Page_0
13. Now in the Quartus II Programmer, select Add File and select your .jic file. Check the Program box next to the .jic file, and push Start