Type: Answers

Area: EMIF

Area: Intellectual Property


IP Product: RLDRAM II Controller with UniPHY

External Memory Interface Handbook: Known Issues

Description

Issue 138581: Volume 3, Chapter 12: Timing Diagrams for UniPHY IP, Version 2.1

Figure 12-18 shows that the avl_size is 0. This value is illegal and should be 1. Everything else in the figure is correct.

Issue 120177: Volume 2, Chapter 4: DDR2 and DDR3 SDRAM Board Design Guidelines, Version 5.0

Figure 4-38. Clock Net Structure for a 64-Bit DDR3 SDRAM UDIMM shows in the notes "(2) The recommended CTT value is 0.1 uF just before VTT." This is incorrect and it should read "VDD", not "VTT".