Device Family: Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V SX, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: Component, HSIO



Why are there bit errors when I perform an RTL simulation of an external serial loopback on Stratix V and Arria V transceiver devices?

Description

You may see bit errors when performing an RTL simulation of an external serial loopback of Stratix® V and Arria® V transceiver devices due to a Mentor Graphics Modelsim® resolution and rounding issue.

Workaround/Fix

To work around this issue, you should set the precision of the simulation to fs.