Device Family: Arria® II GX

Type: Answers

Area: Intellectual Property



How do I access an external PHY using MDIO interface?

Description

There is an error in the Register Map under MDIO Core chapter described in table 13-3 on page 13-5 in the following document:

Embedded Peripheral IP User Guide 

In the table, it is stated that the address offset for MDIO_DEVAD, MDIO_PRTAD and MDIO_REGAD is 0x20, and 0x21 should be used for MDIO_ACCESS. However, they are swapped around in the document and in fact it should have read 0x21 and 0x20 respectively.

NOTE: the register address offsets specified (0x20, and 0x21) are in fact word addresses and the corresponding byte addresses would be 0x80 and 0x84 respectively.

Write Access

Write access to an external PHY can be done by using the MDIO interface as follows:

  1. Perform an Avalon®-MM master write to the MDIO core registers at address offset 0x21, specifying the external PHY device address (MDIO_DEVAD), port-address (MDIO_PRTAD) and register address (MDIO_REGAD).
  2. Issue an Avalon-MM master write of the 32-bit data into the MDIO_ACCESS register offset 0x20.

What happens in the MDIO core?
Once the data is placed into the MDIO_ACCESS register, the MDIO core starts the generation of an MDIO WRITE frames that contains the information provided in registers at offset 0x20 and 0x21. The frame will then be transferred into the target PHY register, the address of which is specified in the MDIO_REGAD (bits [31:16] of the MDIO core register at the offset 0x21).

Read Access

Read access from an external PHY can be done using the MDIO interface as follows:

  1. Perform an Avalon-MM master write to the MDIO core registers at address offset 0x21, specifying the external PHY device address (MDIO_DEVAD), port-address (MDIO_PRTAD) and register address (MDIO_REGAD).
  2. Issue an Avalon-MM master read of the 32-bit MDIO_ACCESS register at offset 0x20.

What happens in the MDIO core?
When a read access to the MDIO_ACCESS register is issued, the MDIO core starts the generation of an MDIO READ frame that contains the information provided in the registers at offset 0x21. As a response to this READ command over MDIO, the external PHY provides the value of the designated register back to the MDIO core. This value is loaded into the MDIO_ACCESS register in the MDIO core at offset 0x20. Thus, it appears as though we were reading the local Avalon-MM register at offset 0x20.

This issue affects both MegaWizard® and SOPC Builder flow.