Device Family: Stratix® III, Stratix® IV E, Stratix® IV GT, Stratix® IV GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: Renewal QDRII / II+ Controller with UniPHY

Why do I see mem_k and mem_k_n clock pair as unconstrained output ports in TimeQuest when I implement QDRII SRAM UniPHY based controller?

Description

Quartus® II software and IP version 10.0 reports mem_k and mem_k_n clock pair as unconstrained output ports because the SDC file generated by the megawizard is missing set_false_path constraint for the clock pair.

Add follwing constraint in the SDC file to fix the issue:

foreach { pin } [concat ] {

                                set_false_path -to [get_ports ]

                }

 

This issue will be fixed in the next version of the Quartus II software and the IP.