Device Family: Stratix® IV E, Stratix® IV GT, Stratix® IV GX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property

IP Product: RLDRAM II Controller with UniPHY

What is the "minimum pulse width timing specification" of the global reset signal for the UniPHY Controller?


Global reset in the UniPHY Controller is connected to PLL areset port. Therefore PLL areset port minimum pulse width (tARESET) for your device will be minimum pulse width timing specification.
For example, tARESET for Stratix® IV and Stratix® V devices are 10ns.