Device Family: Arria® V GT

Device Family: Arria® V GX

Device Family: Arria® V GZ

Device Family: Arria® V ST

Device Family: Arria® V SX

Device Family: Stratix® V E

Device Family: Stratix® V GS

Device Family: Stratix® V GT

Device Family: Stratix® V GX

Type: Answers

Area: EMIF

Area: Intellectual Property


IP Product: RLDRAM II Controller with UniPHY

Can the PCIe Hard IP core and the DDR3 IP core share the same refclk?

Description

It is not recommended to share the refclk between the PCIe® Hard IP core and the external memory interface IP core, which includes all UniPHY and ALTMEMPHY-based controllers. The PCIe interface and the external memory interface need their PLL refclk directly from different dedicated clock input pins.

In order for the memory controller to use the same clock as the PCIe Hard IP core, it would need to cascade the coreclkout signal of the PCIe Hard IP core to the refclk input of the memory IP core. This is not recommended because the additional jitter caused by the global clock routing resource will affect the external memory interface performance.